1. Field of the Invention
The present invention relates to a multiphase clock generator circuit, and more particularly to a multiphase clock generator circuit for generating a plurality of clock pulses that differ in phase.
2. Description of the Related Art
Multiphase clock generator circuit divides a reference clock pulse to generate a plurality of clock pulses that differ in phase. The plurality of clock pulses that differ in phase is used as timing clock pulses for detecting each data in serial data in a receiver circuit for high-speed serial data. Therefore, when the serial data is transmitted at a higher speed, the phase difference of the timing clock pulses for detecting the data must also be reduced. Multiphase clock generator circuits are commonly configured with a circuit for dividing a reference clock pulse, and the reference clock cycle must be made shorter, that is to say, the frequency must be increased in order to reduce the phase difference between the divided clock pulses.
FIG. 1 is a diagram showing the configuration and operation of conventional commonly used multiphase clock generator circuit. In this multiphase clock generator circuit, four D-type flip-flops (D-FF) 11 to 14 are connected in tandem, and the inverse output div2x_qx of the last stage D-FF 14 is connected as feedback to the input data terminal D of the first stage D-FF 11. A clock pulse clk is fed to the first and third stages D-FF 11 and 13, an inverse clock of the clock pulse clk is fed to the second and fourth stages D-FF 12 and 14, and each D-FF latches input data D in response to the rising edge of the clock pulses, and outputs the data to the output data terminals Q and QX. The multiphase clock generator circuit is therefore a divider circuit for dividing the reference clock pulse clk into one fourth frequency.
In accordance with the timing waveform in the diagram, the rising output clock pulses div1_q, div1x_q, div2_q, div2x_q, div1_qx, div1x_qx, div2_qx, and div2x_qx are generated in response to the edges 1 to 8 of the reference clock pulse clk. These eight output clock pulses, which differ in phase, are generated during the interval t1 of the four cycles of the reference clock pulse clk. The frequency of the reference clock pulse clk must therefore be increased and the cycles shortened in order to simply narrow the phase difference of the output clock pulses.
When the multiphase clock generator circuit in FIG. 1 is reconfigured from a four-stage configuration to an eight-stage configuration, the output clock pulses thereof are clock pulses derived by dividing the reference clock into one eighth eight frequency, and 16 output clock pulses that differ in phase are generated in the interval of eight cycles of the reference clock pulse clk. In this case, 16 output clock pulses can be generated in the same interval t1 in FIG. 1 by doubling the frequency of the reference clock pulse clk, and the phase difference of the 16 output clock pulses is ½ the phase difference of the output clock pulses of FIG. 1. In other words, the frequency of the reference clock pulse clk must be increased in this case as well in order to narrow the phase difference of the output clock.
Thus, the multiphase clock generator circuit composed of the divider circuit in FIG. 1 must use a higher speed reference clock in order to generate a multiphase clock with a narrower phase difference. For this reason, a high-speed reference clock must be generated, and the D-FF must have a high-speed operation specification so as to enable the D-FF to operate in response to a high-speed reference clock, leading to higher costs.
A method has furthermore been proposed in prior art in which increasing the speed of the reference clock is avoided by inputting a low-speed clock pulse in which the reference clock has been divided into two cycles to a multistage-connected D-FF, and controlling the flip-flop with reference clock pulses that differ in phase. This method is shown in FIGS. 1 to 4 in Japanese Laid-Open Patent Application No. 2001-318731, for example. In this circuit, a low-speed clock pulse in which the reference clock has been divided into two clock pulses is fed to the data input of the first stage D-FF, and the multistage-connected D-FF sends an input clock pulse in response to the reference clock pulses that differ in phase. It is therefore not necessary to control the circuit operation by a high-speed clock pulse. However, since the circuit is configured to send the low-speed clock pulse to the later stage D-FFs in a sequential manner, each D-FF must be capable of high-speed operation. For this reason, high-speed operation specification is required, leading to higher costs.
In the above-described conventional example, a higher-speed reference clock must be provided in order to narrow the phase difference in a multiphase clock, and the use of a flip-flop capable of operating at higher speeds is required. For this reason, a high-speed device specification and a high-cost manufacturing process is required, leading to higher device costs.